This invention relates to a semiconductor memory chip such as a dynamic random access memory (DRAM) chip and, in particular, to a semiconductor memory chip with On-Die Termination (ODT) function.
A termination circuit is required for good signal integrity at a high frequency operation, as described in U.S. Pat. No. 7,102,200 B2, which is incorporated herein by reference.
As a relevant technique, EP 1 308 849 A2 discloses a memory circuit with an active termination circuit, which is incorporated herein by reference in its entirety. The disclosed circuit comprises a signal terminal, a synchronous input buffer, an asynchronous input buffer and a switching circuit. The synchronous input buffer has an input coupled to the signal terminal. The asynchronous input buffer has another input coupled to the signal terminal. The switching circuit selectively outputs an output of the synchronous input buffer or another output of the asynchronous input buffer in accordance with an operational mode of the memory circuit.
However, according to the disclosure of EP 1 308 849, there might be raised a problem that the synchronous input buffer might malfunction. Hence, there is a need for a circuit that can function with a higher degree of precision.